In recent years, technological advances in the semiconductor industries typified by silicon are large, regardless of industrial and consumer applications, contributing significantly to size reduction, weight reduction, price lowering, and performance advancement of equipment and systems. On the other hand, the request to improving semiconductor devices is not stopped and as a result, higher integration, higher speed, and more sophistication as well as miniaturization are expected. As a measure to meet these requirements, the dimensions of unit elements (e.g., transistors) that constitute a semiconductor device are sometimes miniaturized, thereby increasing the total number of the unit elements to be mounted. The advantage of this measure is increase in operating speed (higher speed) due to miniaturization and increase in function (or, total number reduction of semiconductor devices required) due to high integration. However, higher speed and/or higher integration increase power consumption in the interior of a semiconductor device. As a result, the risk of operation destabilization or damage of a semiconductor device itself becomes large. To reduce this risk, heat dissipation technology (or, cooling techniques) of a semiconductor device is essential.
Many techniques for lowering the operating temperature of a semiconductor device have been developed so far. For example, there is known a technique for cooling a semiconductor device where radiating fins (which are often made of aluminum alloy) are attached to a high-power semiconductor device and air flows are blown to the fins. When the power consumption is comparatively low (e.g., a few watts), this technique is resolvable. However, with the latest semiconductor devices, power consumption has become even greater and thus, the power consumption may reach 100 watts or more in a CPU of a computer or the like. For this reason, with such the high power consuming semiconductor device as described here, if heat dissipation is not sufficient, the temperature of the semiconductor device rises and as a result, thermal runaway or thermal damage may occur. Therefore, it may be said that the upper limit of operation of the semiconductor device is dominated by the heat dissipation technology.
With a “stacked module” formed by stacking a plurality of semiconductor devices, there is an advantage that higher integration can be realized comparatively easily. In such the configuration, power consumption of a semiconductor device positioned in a lower layer increases not only the temperature of this semiconductor device but also the temperature of a semiconductor device located in an upper layer with respect to this semiconductor device. Therefore, when a semiconductor device with a sensitive characteristic to its operating temperature is arranged in an upper layer of the stacked module, there is a possibility that the operation of the entire stacked module becomes unstable. For this reason, in the case of the stacked module, it is preferred that a mounting structure that no heat transfer occurs between the stacked semiconductor devices by cooling only the semiconductor device whose power consumption is large.
As a cooling technique of stacked semiconductor devices (a semiconductor module), conventionally, the mounting structure shown in FIG. 11 has ever been proposed. This figure is published in Patent Document 1 as FIG. 1A.
In FIG. 11, the chip stack 110 is formed by the stack of three semiconductor chips denoted by the reference numerals 110a, 110b, and 110c. Each of the chips 110a, 110b, and 110c comprises channels 175 formed by etching. (In FIG. 11, the reference numeral 175 denotes the typical channels.) The chip stack 110 is designed to be cooled by flowing a fluid (coolant) into the channels 175. This fluid flows in the narrow channels 175 which are formed among the stacked chips 110a, 110b, and 110c. In addition, in the case where the chips 110a, 110b, and 110c are formed by a semiconductor substrate, the thicknesses of the channels 175 are usually several hundreds micrometers or less.
The semiconductor chips 110a, 110b, and 110c are vertically interconnected with TSVs (Through Silicon Vias) indicated by the reference numeral 123.
On the other hand, in a semiconductor module, a wiring board called “interposer” has also been tucked between the stacked semiconductor devices. The required specifications for this interposer may have (1) electrically connecting paths (through electrodes, for example) between the top and bottom surface, and (2) electrical wiring layers (which are also referred to as redistribution layers) on the top or bottom surface, or both of the top and bottom surfaces. If such specifications are satisfied, it is easy to design and make the semiconductor module.